The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device with an on-chip error correction circuit capable of improving the access time and a method for correcting a data error stored therein.
In many semiconductor memory devices, particularly flash memory devices, a cell array is provided that comprises electrically erasable and programmable read only memory cells (EEPROM cells) each having a floating gate. Storing charge in the floating gate of the respective EEPROM cells allows a threshold voltage of each of the EEPROM cells to be electrically altered between low and high level values to represent a logic 1 and a logic 0, respectively. Semiconductor devices utilizing floating gate technology do not have an intrinsic problem with data retention. However, since the high energetic electron injection and emission mechanism used for write and erase operations result in the generation of defects and traps in the tunnel oxide of the devices, reliability problems surface during read and write cycles. Stored electrons can leak away from the floating gate through the tunnel oxide defects and traps. On the other hand, the floating gate slowly gains electrons when the control gate of the EEPROM cell is maintained at the power supply voltage during the read cycle. Charge losses and gains result in an increase and decrease, respectively, in the threshold voltage of the EEPROM cell transistor. These charge losses and gains may result in random bit errors.
In general, an error correcting code/circuit (ECC) is employed for improving the reliability of the flash memory devices. A typical ECC corrects errors using a controller. However, an EEC is needed that is on-chip and capable being used in a card system that does not support the controller. Placing the ECC on a chip is more profitable than placing the ECC in the controller because doing so reduces fabrication costs. On-chip ECC technology is discussed in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 32, No. 5, May 1997, entitled xe2x80x9cA COMPACT ON-CHIP ECC FOR LOW COST FLASH MEMORIESxe2x80x9d, which is hereby incorporated by reference.
FIG. 1 is a block diagram of a conventional semiconductor memory device having an on-chip ECC. The semiconductor memory device of FIG. 1 comprises a memory cell array 10 that stores a plurality of data bits and a plurality of check bits (or redundant bits) corresponding to the plurality of data bits. For simplicity, a well-known NAND type flash memory device will be described as an example. Flash memory cells provided in the NAND type flash memory device are more fully disclosed in U.S. Pat. No. 5,696,717, entitled xe2x80x9cNONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITYxe2x80x9d, which is hereby incorporated by reference.
As illustrated in FIG. 1, the memory cell array 10 is divided into a plurality of input/output (I/O) memory blocks IOMBi (for example, i=1-8) in accordance with an I/O data width (for example, X8). A plurality of word lines WLi are arranged in a plurality of rows through the I/O memory blocks IOMB1-IOMB8, respectively. In each I/O memory block IOMB1-IOMB8, a plurality of bit lines BLm (for example, 512 bit lines) and a plurality of parity bit lines PBLn (for example, 10 parity bit line) are arranged so as to intersect with the word lines WLi of the plurality. In each I/O memory block IOMB1-IOMB8, a plurality of memory cells MC is further provided which are placed at intersections of the word lines WLi and the bit lines BLm and PBLn.
The word lines WLi are connected to a row decoder circuit 12 arranged on the left side of the array 10. The row decoder circuit 12 selects one of the word lines WLi in accordance with externally provided row address signals RA0-RAi. The row decoder circuit 12 drives the selected word line with a word line voltage that is set according to the desired mode of operation (for example, read and write modes of operation). The operation of the row decoder circuit 12 is described in the ""717 patent. The 512 bit lines BLm and 10 parity bit lines PBLn in each I/O memory block IOMB1-IOMB8 are coupled to a sense amplifier circuit 14 placed on the bottom end of the array 10. Although not shown in the drawing, latch-type sense amplifiers, currently used in NAND type flash memory and DRAM devices, are provided in the sense amplifier circuit 14 so as to correspond to the number of the bit lines and parity bit lines in each I/O memory block. For example, the number of sense amplifiers corresponding to each of the I/O memory blocks IOMB1-IOMB8 is 522 (512+10). An example of the latch-type sense amplifier used in NANID flash memory devices is disclosed in U.S. Pat. No. 5,216,633, entitled xe2x80x9cNONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ACCESS CODE CIRCUITRYxe2x80x9d, which is hereby incorporated by reference.
The respective sense amplifiers corresponding to each block IOMB1-IOMB8 sense and amplify 512 data bits and 10 check bits from the corresponding I/O memory block through the corresponding bit lines BLm and parity bit lines PBLn, and then latch the sensed data and check bits therein.
A column pass gate circuit 16 is connected to the sense amplifier circuit 14. The column pass gate circuit 16 operates under the control of a column decoder circuit 18. Error correction circuits 20 respectively corresponding to the I/O memory blocks IOIMB1-IOMB8 are connected to the column pass gate circuit 16. The 512 data bits and 10 check bits read out from each of the I/O memory blocks IOMB1-IOMB8, that is, latched in the sense amplifier circuit 18, are sequentially transferred to the corresponding error correction circuit 20 through the column pass gate circuit 16 responsive to column decoder circuit 18. The operation of these circuits will be more fully described later.
FIG. 2 is a block diagram of the error correction circuit 20 illustrated in FIG. 1. The error correction circuit 20 illustrated in FIG. 2 corresponds to one of the 8 I/0 memory blocks IOMB1-IOMB8 and comprises a syndrome generator 22, an error detector 24, and an error corrector 30. It should be obvious to one skilled in the art that all error correction circuits 20 shown in FIG. 1 are configured as shown in FIG. 2. In FIG. 2, the error correction circuit 20 is based on the Hamming code (2rxe2x89xa7m+r+1, wherein m is the number of data bits and r is the number of check bits or redundant bits generated by the generator polynomial g(x)=x10+x3+1).
FIG. 3 is a timing diagram of the error correction circuit illustrated in FIG. 2. Operation of reading out data from the memory cell array 10 will be described more fully below with reference to FIGS. 1 to 3. For simplicity, the data read operation of only one I/O memory block will be described.
The operation of reading out data is divided into a first and a second cycle. During the first cycle, 522 bits of an ECC word, which corresponds to a selected page (or a word line) of the I/O memory block, for example, IOMB1, are sequentially transferred to the syndrome generator 22 through the switch circuit 26 (that is, the column pass gate circuit 16). The syndrome generator 22 produces 10 syndrome bits responsive to the 522 bits of the ECC word. The 10 syndrome bits thus produced from the syndrome generator 22 are used as an address for correcting a 1-bit error in the data bits of the selected page and are decoded by means of the error detector 24. In FIG. 2, the column pass gate circuit 16 of FIG. 1 is illustrated by the switch circuits 26 and 28 that operate exclusively of each other during the first and second cycles.
During the second cycle, the signal (address information for the error) decoded by the detector 24 and the 512 data bits latched in the sense amplifier circuit 14 are sequentially applied to the error corrector 30, which is embodied by an exclusive-OR gate circuit. The 512 data bits thus corrected are provided externally through a corresponding I/O circuit 32. For example, in the event that the signal from the detector 24 corresponding to a data bit currently transferred to the corrector 30 is at a logic 1, it means that the data bit is erroneous. Thus, the erroneous data bit is transferred to the corresponding I/O circuit 32 after being corrected by the corrector 30. If the signal from the detector 24 is at a logic 0, it means that the data bit is not erroneous. Thus, the data bit is transferred to the corresponding I/O circuit 32 without any error correction ocurring at the corrector 30.
According to the conventional semiconductor memory device with the above described error correction circuit scheme, only a bit error in the 512 data bits of a selected page can be detected and corrected. Further, 522 clock cycles for controlling the switch circuit 26 (FIG. 2) are required during the first cycle of the read mode of operation in which an error place in the 512 data bits is detected as above described. This causes an increase in the access time of the flash memory device. Therefore, to realize a high-speed memory device having a high reliability requires reducing the access time and improving the error correction efficiency.
It is therefore an object of the present invention to provide a semiconductor memory device with an on-chip error correction circuit capable of improving the access time.
It is another object of the invention to provide a semiconductor memory device with an on-chip error correction circuit capable of correcting at least two erroneous bits in the data bits that correspond to an input/output memory block.
It is still another object of the invention to provide a method for correcting a data error in a semiconductor memory device.
According to one aspect of the present invention, there is provided a method for correcting an error in a semiconductor memory device having a memory cell array including a plurality of data bits and plurality of check bits corresponding to the plurality of data bits. The plurality of data bits and the plurality of check bits are divided into at least a first and a second group. The method comprises sensing the plurality of data bits and the plurality of check bits from the memory cell array; simultaneously receiving the data and check bits of the first group and the data and check bits of the second group to generate a first and a second set of syndrome bits corresponding to the first and the second group of the data and check bits, respectively; decoding the first and the second set of syndrome bits to detect an error in the data bits of the first and the second group, respectively, and generating a first signal indicative of the presence or absence of the error in the data bits of the first group and a second signal indicative of the presence or absence of the error in the data bits of the second group; and alternatively receiving the data bits of the first and second group and correcting the error in the data bits of the first group responsive to the first signal and the error in the data bits of the second group in response to the second signal.
According to another aspect of this invention, there is provided a semiconductor memory device comprising a memory cell array for storing a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits, the plurality of data bits and the plurality of check bits being divided into at least first and second groups; means for reading out the plurality of data bits and the plurality of check bits from the memory cell array; and means for correcting a first error in the data bits of the first group and a second error in the data bits of the second group, respectively. The means for correcting receives the data and check bits of the first group and the data and check bits of the second group in parallel, generates first and second syndrome bits respectively corresponding to the first and the second group of the data bits, and corrects the first error in the data bits of the first group and the second error in the data bits of the second group responsive to the first and the second syndrome bits, respectively. An input/output circuit is further provided that outputs the data bits of the first and the second group alternatively outputted from the means for correcting. The means for correcting comprises a first error correction circuit for correcting the first error in the data bits of the first group and a second error correction circuit for correcting the second error in the data bits of the second group, the first and second error correction circuits being commonly coupled to the input/output circuit, wherein the first error correction circuit comprises a first syndrome generator for sequentially receiving the plurality of data and check bits of the first group and generating the first syndrome bits responsive thereto; a first detector for decoding the first syndrome bits to detect the first error in the data bits of the first group and generating a first signal indicative of the presence or absence of the first error; and a first corrector for sequentially receiving the data bits of the first group and correcting the first error in the data bits of the first group responsive to the first signal indicative of the presence or absence of the first error; and wherein the second error correction circuit comprises a second syndrome generator for sequentially receiving the plurality of data and check bits of the second group and generating the second syndrome bits responsive thereto; a second detector for decoding the second syndrome bits to detect the second error in the data bits of the second group and generating a second signal indicative of the presence or absence of the second error; and a second corrector for receiving the data bits of the second group, and correcting the second error in the data bits of the second group responsive to the second signal indicative of the presence or absence of the second error.